Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), may be programmed with configuration data (sometimes referred to as a configuration bitstream) to provide various user-defined features. In certain applications, configuration data may be programmed into an external non-volatile memory such as a flash memory. The configuration data may be loaded from the external non-volatile memory into the PLD and programmed into volatile configuration memory of the PLD.
After a PLD has been configured through the programming of configuration data into the configuration memory, the PLD may be reconfigured through the programming of new or different configuration data into the configuration memory. For example, in one prior approach, a PLD reconfiguration process may be performed in response to the toggling of an external pin of the PLD. In another approach, a PLD may be reconfigured in response to an instruction received by the PLD through, for example, an external joint test action group (JTAG) port (e.g., employing standards such as Institute of Electrical and Electronics Engineers (IEEE) 1149.1 or 1532 standards).
However, in each of these prior approaches, toggle signals or instructions must be provided to the PLD from external hardware in order to trigger a reconfiguration. But external hardware may not always be apprised of processes occurring in the PLD and therefore may not always know when a reconfiguration should be performed. External hardware may also be unaware of the location of new configuration data to be provided to the PLD for reconfiguration. Accordingly, there is a need for an improved approach to the reconfiguration of a PLD that, for example, does not rely on the PLD receiving external signals or instructions.